1. Technical Field
The present disclosure relates to a process for manufacturing semiconductor devices, such as super-barrier rectifiers.
2. Description of the Related Art
As is known, the recent family of super-barrier rectifiers (SBRs), namely, adjustable field-effect rectifiers (AFERs, see for example U.S. Pat. No. 8,148,748) envisages the use of regions typical of MOSFET transistors and the addition of a so-called “pocket” or “probe” region so as to reduce the negative resistance and at the same time have a high recovery speed, even at high frequency, and in this way reduce the problems of electromagnetic interference.
With this device, it is important for the distance between the channel and the “pocket” or “probe” to be as small as possible, but for the two regions not to overlap. Consequently, the channel implant has lateral dimensions and corresponding tolerances that are very critical.
Since in this technology the channel is lithographically defined, the performances of the device are limited by the very accuracy of the lithographic process.
By virtue of the probe implantation being made subsequently and in regions complementary to the channel regions, alignment errors occurring in the various masking levels add together, jeopardizing the final result or, at the very least, reducing the performances of the finished device.
On the other hand, the current trend to miniaturization uses, at least in certain applications, an increase in the circuit density so that it becomes important to reduce both the spacing and the overlap between the adjacent regions.
For a better understanding of the problem referred to above, reference may be made to FIGS. 1-10, which show an adjustable field-effect rectifiers (AFER) diode developed by the present applicant.
FIG. 1 shows a cell 2 belonging to an AFER diode 1, generally comprising a plurality of cells 2, adjacent to each other and formed by strip-like shaped regions extending perpendicularly to the drawing plane. The AFER diode 1 is formed in a substrate 3 of semiconductor material of an N− type, which forms a first drain region. A second drain region of an N+ type (not shown) may extend underneath the substrate 3, and a drain metallization (not shown either) may extend underneath the second drain region.
Each cell 2 comprises a well region 4, of a P type; source regions 16, of an N+ type; and a probe region 5, of an N type, facing a surface 6 of the substrate 3.
A gate oxide layer 11 extends over the surface 6, and a gate region 12 extends over the gate oxide layer 11. The gate oxide layer 11 and the gate region 12 have, in each cell 2, an opening 13, and a portion 14a of a conductive (metal) region 14 arranged on top of the gate region 12 extends in the opening 13. The portion 14a of the metal region 14 extends also partially within the substrate 3 and is here adjacent to the source regions 16 and to the well region 4.
In detail, the source regions 16 extend on the two sides of, and directly adjacent to, the portion 14a of the metal region 14. The well region 4 comprises a deep portion 9, which is more doped, extending underneath the portion 14a of the metal region 14, and two surface portions (forming channel regions 10), which face the surface 6 and are each arranged on a side of a respective source region 16. The channel regions 10 are each adjacent to a respective probe region 5 (one belonging to the cell 2 itself, the other to the adjacent cell 2). The probe region 5 is deeper than the channel regions 10, but is arranged closer to the surface than the deep portion 9 of the well region 4.
In practice, the portion 14a of the metal region 14 directly contacts and electrically connects together the gate region 12, the source regions 16, and the deep portion 9 of the well region 4. A silicide layer 15, for example of titanium, may extend underneath the metal region 14, over the gate region 12 and on the sides of the opening 13.
The AFER diode 1 is obtained as shown in FIGS. 2-9.
Initially (FIG. 2), the active area is prepared: the gate oxide layer 11 and the gate region 12, here of polysilicon, are formed on the substrate 3.
Then (FIG. 3), a poly mask 20, of resist, is formed on the gate region 12 and has a window 21 where the opening 13 is to be formed. Using the poly mask 20, the exposed portion of the gate region 12 is removed to obtain the window 13, and, in the substrate 3, an implantation of dopant species of a P type, for example a boron implantation, is carried out so as to form a p-well region 17.
Next (FIG. 4), using the same poly mask 20, a tilted implantation is carried out with dopant species of an N++ type, for example arsenic, so as to form an enriched layer 22, which, thanks to the tilted implantation, extends, with its peripheral portions, underneath the gate region 12.
Then (FIG. 5), the gate oxide layer 11 and the substrate 3 are etched and removed in the area underneath the window 21 (and thus the opening 13) to form a microtrench 18. In this way, also part of the enriched layer 22 is removed, but underneath the gate region 12, the peripheral portions of the enriched layer 22 remain, to form the source regions 16.
Next (FIG. 6, an implantation of dopant species of a P type (e.g., BF2) is carried out inside the p-well region 17, to form a thin layer 23 of a P type, more doped than the p-well region 17 and not shown for simplicity in the subsequent figures.
After removal of the poly mask 20 (FIG. 7), a channel mask 24 of resist is formed. The channel mask 24 has a window 25 that is ideally centered with respect to the window 21 of the poly mask 20 (and thus to the opening 13), but is wider, so as to expose, in addition to the microtrench 18 and the opening 13, also the top surface of the two portions of the gate region 12, laterally to the opening 13. Then, dopant species of a P type are implanted to provide the channel regions 10 in the substrate 3, laterally to the opening 13, and an enriched area 26 within the p-well region 17. However, since the channel implant has a lower dose than the well implant (typically the difference is of two orders of magnitude, 1012 for the channel implant and 1014 for the well implant), the channel implant does not modify the concentration of the p-well region 17. Consequently, the enriched area 26 is no longer shown in the subsequent figures. Ideally, the width of the channel regions 10 should be the same; however, on account of the inevitable misalignments between the poly mask 20 and the channel mask 24, in practice they have a different length.
After removing the channel mask 24, a probe mask 27 is formed (FIG. 8). Probe mask 27 is ideally complementary to the channel mask 24 and covers the gate region 12 on top of the p-well region 17 and the channel regions 10. Dopant species of an N type are then implanted to form the probe regions 5 laterally to each channel region 10. Ideally, the probe regions 5 are immediately adjacent to the channel regions 10, even though they may extend to a greater depth, but the misalignment between the channel mask 24 and the probe mask 27 may cause a spacing between one channel region 10 and the adjacent probe region 5, on one side, and an overlapping between the two regions 10, 5, on the opposite side.
After removing the probe mask 27, the silicide layer 15 (FIG. 9) and then the metal region 14 (FIG. 10) are formed.
After the thermal steps for activating the dopant species, the structure of FIG. 1 is obtained, wherein the deep portion 9 of the well region 4 has a non-uniform doping, and the well region 4 embeds the channel regions 10.
In AFER diodes of this type, the lateral dimensions are very small and critical so that alignment errors referred to above may considerably affect the operation of the diode and may use compromises for relaxing design rules and tolerances.
For example, in devices produced by the present applicant, the probe region 5 and the opening 13 may have a width of approximately 350 nm, and the distance between the opening 13 and the adjacent side edge of the probe region 5 may be approximately 250 nm, so as to ensure a channel length of approximately 100 nm, with a lateral dimension of the source region 16 of approximately 150 nm. The length of channel (width of the channel region 10, between the source region 16 and the probe region 5) may be 100 nm.
As indicated above, with the described manufacturing technique, criticality derives from the fact that the channel implant (using the channel mask 24) and the probe implant (using the probe mask 27) are aligned, with two different photo-techniques, to the contact previously opened in the gate region 12 (opening 13 obtained using poly mask 20), on the basis of the precision degree used for the channel and probe photo-techniques.
To achieve this precision, various solutions have been suggested, such as: use of exposure systems for VLSI technologies, with maximum misalignments within 20 nm; execution of dimensional checks in all the steps; use of feedback systems for automatic compensation of the process drift; and use of golden tools.
However, these actions have an impact on the production flow in terms of costs and cycle times.